about Verilog IP block memory

The name of the picture


about Verilog IP block memory



I'm using vivado 2016.4 Verilog,



I have implemented a RISC processor and I want to connect this with 2 BRAMs.



One BRAM is an Instruction Memory and another is Data Memory. (external memory)



I tested the top module connect with Inst.Mem and Data.Mem which was made by myself before, and test result is correct.



but, module with include same source code (.v files) and substitute myMemory to IP catalog -> Block Memory Generator, test result is not correct.



some output signals delayed 1 or 2 clock period.



what is my problem? and how can i correct this?









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